Recently, researchers have been directing their attention toward developing digital logic circuits which combine bipolar and CMOS technologies in a single integrated circuit. The marriage of bipolar and CMOS technologies is particularly advantageous since the superior aspects of each may be exploited and combined to yield optimal circuit performance.
For instance, CMOS circuits have the advantages of extremely low quiescent power consumption, rail-to-rail output capability, high density and a very high input impedance. Bipolar logic circuits, on the other hand, are useful in driving large capacitance loads, have very fast switching capabilities and feature better performance over temperature and power supply. These attributes have lead to the development of a family of BiCMOS digital logic circuits which employ bipolar transistors to drive output loads while utilizing CMOS devices to perform the basic logic functions on the received input signals. Digital logic circuits implemented using BiCMOS technology are discussed in "BiCMOS Technology and Applications", edited by Antonio R. Alvarez, Kluwer Academic Publishers, 1990, Chapter 5 (pages 165-200). Examples of BiCMOS binary logic circuits are also disclosed in U.S. Pat. Nos. 4,701,642; 4,871,928; 4,845,385; 4,703,203; 4,636,665; 4,779,014; and 4,808,850.
Emitter-coupled logic (ECL) is a very well understood family of bipolar logic circuitry. Its popularity stems from the fact that ECL provides the faster bipolar logic available. However, the main drawback is the fact that bipolar ECL gates also consume the most power of conventional logic technologies. Thus, it would be desirable to integrate the high switching speed capabilities of conventional bipolar ECL along with the high-density, low-power characteristics of CMOS circuits. A hybrid ECL/MOS family of logic circuits would be capable of taking advantage of the strengths of the individual technologies.
Unfortunately, past attempts to create BiCMOS ECL logic gates have not been entirely successful. BiCMOS logic gates often have difficulty matching the temperature and supply dependence of ECL circuitry. The complicated temperature dependence of the bipolar transistor counts in large part for this difficulty to interface ECL circuitry with CMOS logic stages. While the problem of the bipolar transistor's negative temperature coefficient has been circumvented in fully bipolar ECL logic devices (e.g., the Motorola 100K ECL family), merged ECL/MOS circuits have not been as successful.
Therefore, what is needed is an integrated circuit (IC) combining CMOS and bipolar technologies which implements an ECL compatible logic function. Such as circuit should be capable of compensating for the negative effects of process and temperature variations which are an ordinary part of an IC's operating environment. As will be seen, the present invention provides a novel BiCMOS ECL gate possessing these characteristics. In addition, the invented ECL logic gate features the ability to vary the output voltage swing as well as control the total power dissipation of the circuit.